“Source Synchronous Clocking” (SSC) refers to a data interface between a transmitter and a receiver, where the transmitter launches data accompanied by clock, and the clock has a well defined phase with respect to the data. This type of interface is commonly found in communications equipment, such as the interface between a serializer/deserializer (SerDes) and a Framer.
In some cases, the receiver can use the transmitter clock to sample the data, provided that the phase between clock and data is property controlled. However in some cases, the receiver has its own local clock domain, at a commensurate frequency but at an unknown phase with respect to the transmitter clock. (Two clocks are deemed commensurate when the ratio of their frequencies is a rational number). In these cases the receiver must synchronize the transmitter data to the receiver clock domain. Therefore, some way of evaluating the relationship between the phase of the transmitter clock and the receiver clock is required. If multiple phases of the receiver clock are available, then the optimal phase can be chosen to accomplish the handoff of data between transmit and receive clock domains.
The transmitter clock frequency may be at the full symbol rate, where a single (e.g. falling) edge of the dock is used to sample the data, or it may be at half of this frequency, in a so-called Dual Data Rate (DDR) interface.
A need has been recognized in connection with effecting tangible improvements in the types of devices described above.